The system allows to readout GEM detector using GEMINI Asic, available on 32D board (32 channels, digital output). The system implement a 256 channels TDC on a dual-fpga system. The TDC has a resolution on 0.5 ns and allows to perform both ToF (time of flight) and ToT measures symultaneusly.
The ASIC implement the analog front-end, the comparator, and the threshold regulation.
The FPGA board measure the ToF in respect to a T0 signal that can be generated inside the board or provided externally by a LEMO connector.
The FPGA board is interfaced to the readout PC using 1 Gbps ethernet allowing a maximum readout speed of about 10 Mevent/s.
The maximum imaging pixel count for a single board is 256 pixel, the resolution can be increased by center of mass or more complex tecniques.
The ToT measure is proportional to the energy released by the interaction on the GEM detector, indeed it is possble to make spectroscopy measuraments or slice the 2D image in function of the energy.
The readout is always performed in list mode. The software manipolate the list to extract information like Time Of Flight, energy spectrum, images, etc…
The board has a 30×30 mm center hole used to reduce the mass on the beam when used as beam monitor on high energy beam or when used as upstream detector in order to reduce the scattering to the downstream detector.
The FPGA board can be powered by a single 12v supply
- 256 pixel indipendently readout
- Time over threshold and time of flight measuraments.
- 256 TDC channels with 0.5 ns resolution
- 4ns double hit resolution
- Up to 10 Mcps on whole detector
- Up to 5 Mcps on single pixel (limited by the ASIC)
- 1 Gbyte local memory
- 1 Gbps ethernet connectivity
- Realtime monitor software with advanced analysys features
- List mode data dumping
- External (on lemo) and internal T0
- External programmable VETO
- Single channel programmable VETO
- External busy output
- 12V, 1.5 A
- Windows software and drivers
The system is composed by two stacked board. The board on front is the interface board with ethernet connectivity and LEMO connectors. The board on the back is the TDC board. The ASIC are plugged as micro-modules (32D) on the bottom of the TDC board.
Readout stack with 8×32 channels GEMINI detector boards and GEM PADs.
Example of GEM detector design to be coupled with GEM256E
The software for Windows allows the configuration of managing of the system. All operation parameters of the ASIC (i.e. channel threashold, gain, veto) and DAQ parameters (like T0 source, T0 frequency, etc) can be configured by this interface.
The software receive data from the FPGA and rencostruct in live, images and histograms. The software is capable to store data on disk in form of list while, at the same time, it perform live data processing.
The software is capable to perform the following online analysys:
- Image recostruction based on the pixel remap matrix that allows to readout any shape detector even if not rectangular
- Display integral and realtime counts image
- Display integral and realtime ToT image
- Display images sliced by ToT
- Display images slliced by ToF
- Display TOF histogram for each channel
- Display TOT histogram for each channel
- Display TOT/TOF sum histogram applying calibration
- Realtime calculation of statistic information like, input rate, T0 rate
Energy spectrum based on TOT and 2D image recostruction in X-RF application using a GEM detector
2D image sliced by energy in X-RF application using a GEM detector. Each slice contains the spatial information of the pixel having signal in the energy window allowing the spatial identification of material using energy peak
In principle can be coupled with any asic capable to produce a TOT (time over threshold) LVDS or CMOS signal.
The system is designed to opeate with GEMINI ASIC has been developed by the Microelectronic Group at University of Milano-Bicocca in collaboration with the IFP-CNR and the LNF INFN institutions. It has been thought to be dedicated to Triple GEM detector structures, but it can easily be re-adapted for detectors with similar performance. It is made of 16 detecting channels, each including a Charge Sensitive Preamplifier (CSP) with auto-tuned feedback capacitor and a Discriminator with a channel independent programmable threshold. The automatic calibration feature is provided in background by a dedicated unit, able to reach a feedback capacitor resolution less than 5%. The comparator programmable threshold is realized through the inclusion of a 9-bit R-2R Ladder DAC, with 1.2 mV LSB and 500 mV (or externally set) full-scale. The 9-bit threshold digital word can be set through an on-chip I2C interface, with dedicated registers. Two output signals for each channel are generated. The main output is digital. In fact, an LVDS signal is available for event counting rate up to 5 Mcps. In addition, making off-chip spectroscopy measures or checking the detector signal is possible via the analog CSP output.
In Figure the GEMINI read-out scheme is depicted, together with a channel main signals example plot. The SoC is made of 16 channels where, with the inclusion of a Charge-Sensitive Preamplifier (CSP), the signal from the detector is converted from charge domain to voltage domain. Then, the Discriminator (DISC) compares the CSP output voltage level with a threshold, set by an R-2R Resistive DAC and specific for each detecting channel, generating the Event Detection output signal. This output is then converted into LVDS standard through a dedicated driver. The channel also produces an analog output signal, which is the buffered CSP output.
The Charge-Sensitive Preamplifier
The CSP composes of a Single Stage Telescopic Operational Amplifier (Opamp) with the CF capacitor and the RF resistor connected in feedback. The Q-V Gain imposed by specifications, i.e. 1 mV/fC, sets directly CF to 1 pF. With a 40 pF CD (pixel capacitance) maximum value, dimensioning the Opamp to obtain 58 dB DC-Gain and 80 µVRMS of in-band integrated noise means that the Signal-to-NoiseRatio lies in a range between 19 dB and 43 dB, with minimum (30 fC) and maximum (500 fC) charge respectively, while the charge collection efficiency is 98%.
As regards the DISC, the main target is to reduce the input stage offset, in order to achieve the sensitivity and the detection jitter required (3 fC and 9 ns respectively). This means that the maximum tolerated offset is 3 mV after the CSP conversion, as well as for the R-2R Resistive DAC LSB, representing the minimum threshold. Designing the DISC with a mirrored structure and exploiting the inter-digitated layout technique allows to limit the offset within specs. Dealing with the threshold, the 9-bit R-2R Resistive DAC has a 1.2 mV LSB and 500 mV full-scale, set from the external. The input digital words, independent for each channel, are stored into dedicated registers managed from the I2C interface.
nTOF (CERN) beam monitor: The FPGA based program is able to create the pictures of the beam spot in the different energy ranges Here the 9 energy slices ranging from 10 to 5 Mev.